Handling large amount of Data between modules in Verilog

I tried josyb solution but wasn't able to let it work.

How to index the internal signals that now have a double index?

If I declare it like this:

--- Quote Start ---

module tmp2(A[1:0],Y);

input [7:0]A;

wire [7:0] A;

output [7:0] Y;

wire [7:0] Y;

assign Y = A+{A,1'b1};

endmodule

--- Quote End ---

it looks like A is a 2bit signal

If I declare it like this:

--- Quote Start ---

module tmp2(A[7:0],Y);

input [1:0]A;

wire [1:0] A;

output [7:0] Y;

wire [7:0] Y;

assign Y = A+{A,1'b1};

endmodule

--- Quote End ---

I get an error

Any hint?