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Altera_Forum
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15 years ago

Handling large amount of Data between modules in Verilog

Hi all, I want to handle large amounts of data between Modules. I somehow need to connect up to 1024 inputs and 1024 outputs which are [16:0] width each. For the moment, the only solution ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Alas, I tried it in Quartus II after reading FvM's post and it doesn't work. Looks like Verilog is quite limited , so stepping up to SystemVerilog seems to be the advice ... so I'll have to look for a good book on SystemVerilog