Handling large amount of Data between modules in Verilog

System Verilog brings also structurized data types (e.g. arrays) for module interfaces, but standard Verilog hasn't it. So you have to represent the connection by a large [17*1024-1..0] "flattened" vector. But that's no problem for the design compiler, bad readability is probably the main drawback.

You'lll need a rather large FPGA to have about 17500 internal signals, and also a considerable amount of routing resources. Did you verify, that the design is feasible, apart from the particular module connection problem?