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Altera_Forum's avatar
Altera_Forum
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15 years ago

Handling large amount of Data between modules in Verilog

Hi all, I want to handle large amounts of data between Modules. I somehow need to connect up to 1024 inputs and 1024 outputs which are [16:0] width each. For the moment, the only solution ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm not a Verilog expert (not even close as I use VHDL for about five years now, after using AHDL for over 10 years) but I checked Thomas & Moorby's 'The Verilog Hardware Description Language' and looking into a MegaWizard generated .v file, I feel it should work like this 

module ttt (
	inp_fre  ,
	... ,
	... ) ;
	input	  inp_fre;
   ...
endmodule