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Altera_Forum
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10 years ago

Generating 400MHz external clock (Cyclone V)

Hello,

I'm trying to generate a 400MHz clock signal from my Cyclone V in order to drive the clock input for an external ADC, but I'm getting severe attenuation on the clock signal. Details:

-I'm using the PLL megacore wizard, with output frequency set to 400MHz, and operation mode set to LVDS. Input clock is 50MHz.

-The LVDS PLL output clock is going to diffio_tx_p&n pins (but I've also tried outputting a single-ended clock to a gpio pin and got similar problems).

-I'm measuring the output clock using a 1GHz scope and 15pf probes to probe these diffio pins. The output clock works well for lower frequencies such as 60MHz, but attenuates as frequency increases. By the time I hit 400MHz the Vp-p of the out clock is only 100mv but I need it to be >500mv.

Question:

Are there different pins on this fpga I should be using instead that would drive those 400+MHz frequencies, or what else might I be doing wrong?

Thanks

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  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thanks everyone for your suggestions.

    Firstly, the scope was set by default to only 250MHz bandwidth so I changed this once realizing it to 500MHz. I also changed to 500MHz rated probes and improved to 320mV p-p @400MHz on the scope.

    When the datasheet says PLL can support up to 667MHz, at what p-p swing is this supposed to be?

    I can improve my probing method further with modifications to the board, but would like to know what I can expect for max p-p swing on this. The adc requires minimum 500mV swing for its clock but we don't have it broken out for the fpga, so we can't directly test it
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    ah_zhi02 is right. The Cyclone V PLL can support up to 667MHz clock output according to the device datasheet. Thus, there should not be issue achieving 400MHz output.

    --- Quote End ---

    That is actually not quite correct. The clock output from the PLL still has to pass through the IO circuitry like any other IO pin, so the IO switching limitations for the speed grade of the device apply (there is a footnote in the datasheet which mentions exactly this). The fastest speed grade (C6) can achieve 420MHz rate, the slower devices are rated at lower than 400MHz speeds.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    The adc requires minimum 500mV swing for its clock ...

    --- Quote End ---

    You would not normally clock the ADC from an FPGA PLL output. You would generally design a low-jitter clock source and have that clock source clock both the ADC and FPGA. For example, see the analysis for this 1GHz ADC board;

    https://www.ovro.caltech.edu/~dwh/carma_board

    I'm not saying that clocking the ADC from an FPGA will not work, but that it is risky, since the jitter on the FPGA PLL output clock will depend on the logic inside the FPGA, and temperature variation of the FPGA due to signal processing work-load could affect the PLL output phase, which is an issue in some applications, eg. coherent processing using multiple boards.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Dave is quite correct on this point. Look at the worst case jitter specifications for the PLLs in the FPGA and you'll see they're pretty horrendous.