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Altera_Forum
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11 years ago

Generating 400MHz external clock (Cyclone V)

Hello, I'm trying to generate a 400MHz clock signal from my Cyclone V in order to drive the clock input for an external ADC, but I'm getting severe attenuation on the clock signal. Details: ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Dave is quite correct on this point. Look at the worst case jitter specifications for the PLLs in the FPGA and you'll see they're pretty horrendous.