Generating 400MHz external clock (Cyclone V)

Thanks everyone for your suggestions.

Firstly, the scope was set by default to only 250MHz bandwidth so I changed this once realizing it to 500MHz. I also changed to 500MHz rated probes and improved to 320mV p-p @400MHz on the scope.

When the datasheet says PLL can support up to 667MHz, at what p-p swing is this supposed to be?

I can improve my probing method further with modifications to the board, but would like to know what I can expect for max p-p swing on this. The adc requires minimum 500mV swing for its clock but we don't have it broken out for the fpga, so we can't directly test it