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Altera_Forum
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10 years ago

Generating 400MHz external clock (Cyclone V)

Hello,

I'm trying to generate a 400MHz clock signal from my Cyclone V in order to drive the clock input for an external ADC, but I'm getting severe attenuation on the clock signal. Details:

-I'm using the PLL megacore wizard, with output frequency set to 400MHz, and operation mode set to LVDS. Input clock is 50MHz.

-The LVDS PLL output clock is going to diffio_tx_p&n pins (but I've also tried outputting a single-ended clock to a gpio pin and got similar problems).

-I'm measuring the output clock using a 1GHz scope and 15pf probes to probe these diffio pins. The output clock works well for lower frequencies such as 60MHz, but attenuates as frequency increases. By the time I hit 400MHz the Vp-p of the out clock is only 100mv but I need it to be >500mv.

Question:

Are there different pins on this fpga I should be using instead that would drive those 400+MHz frequencies, or what else might I be doing wrong?

Thanks

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Your scope probably does not have enough bandwidth.

    The Fourier Transform of a (perfectly symmetric) square wave has odd harmonics

    http://mathworld.wolfram.com/fourierseriessquarewave.html

    so your 400MHz square wave has a fundamental at 400MHz, and the first harmonic at 1.2GHz. Hence, your 1GHz bandwidth scope attenuates the harmonics, and makes your square wave look like a sinusoid.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I concur with Dave's observation about scope bandwidth. Also, your 15pf looks like about 26 ohms at 400Mhz, a stiff load for an FPGA output.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thank you Dave,

    It does look like a sine wave yes, but shouldn't the amplitude of the fundamental 400MHz sine wave still not be severely attenuated with 1GHz scope? The fundamental should have higher amplitude than the overall square wave.

    edited: changed first harmonic to fundamental
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    It does look like a sine wave yes, but shouldn't the amplitude of the fundamental 400MHz sine wave still not be severely attenuated with 1GHz scope?

    --- Quote End ---

    The quality of the signal you observe depends on your ability to probe the circuit with a scope probe, with a ground return path right next to it.

    If I want to capture clean looking waveforms for documentation, I will generally solder a wire loop to ground (eg., decoupling cap pad) next to the probe point, and wrap that wire around the scope probe tip. That provides the least inductance, without having to use fancy probe tips.

    If you can see a 100mVpp sinusoid, then the LVDS receiver on the ADC clock input pin should still work ok. If the ADC is not working now, chances are you have another issue you have yet to find :)

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi sio9ath,

    You can try to boost the LVDS VOD and pre-emphasis settings to see if can help to get higher amplitude or large output eye at your TX.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    So, is the 1GHz the oscilloscope's bandwidth? What is the sampling rate then? Maybe the scope has a "periodic signal" mode, which can improve the sampled waveform in your case.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi si09ath,

    Perhaps you might want to share the screen shot so that everyone could have better idea what you are facing.

    I don't think there are any hardware limitation on FPGA to output 400Mhz but if you would like to confirm that, instead of output using ALTLVDS. Use the SERDES to output a repeated 10101010

    Also I don't think there is anything wrong with a 1 GHz scope unless is setting. Try pressing the AUTO button then let the scope final best setting to probe. Then check the board if there if there are any cap
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    ah_zhi02 is right. The Cyclone V PLL can support up to 667MHz clock output according to the device datasheet. Thus, there should not be issue achieving 400MHz output.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    I concur with Dave's observation about scope bandwidth. Also, your 15pf looks like about 26 ohms at 400Mhz, a stiff load for an FPGA output.

    --- Quote End ---

    Here is a link to an article discussing this kind of measurements: http://www.eetimes.com/document.asp?doc_id=1272404

    We always use this technique to probe our circuits.

    Regards,

    Josy
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thanks everyone for your replies,

    Based on what you've said I'm sure my readings can be further be improved via better probing. First off, by switching to a better probe (500MHz rated & 8pF) and realizing the scope was set to default BW of 250MHz then changing this to 500MHz, the p-p swing increased to 300mV @400MHz. My ADC requires minimum 500mV p-p swing for its clock input.

    When the datasheet says PLL can support 667MHz, at what p-p swing is this? I can't test it cleanly with the ADC yet (need different connectors) but it'd be good to know that >500mV is possible @400MHz.

    Thanks