--- Quote Start ---
The adc requires minimum 500mV swing for its clock ...
--- Quote End ---
You would not normally clock the ADC from an FPGA PLL output. You would generally design a low-jitter clock source and have that clock source clock both the ADC and FPGA. For example, see the analysis for this 1GHz ADC board;
https://www.ovro.caltech.edu/~dwh/carma_board I'm not saying that clocking the ADC from an FPGA will not work, but that it is risky, since the jitter on the FPGA PLL output clock will depend on the logic inside the FPGA, and temperature variation of the FPGA due to signal processing work-load could affect the PLL output phase, which is an issue in some applications, eg. coherent processing using multiple boards.
Cheers,
Dave
Honored Contributor
