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Honored ContributorFractional N PLL implimentation in IP possible on Cyclone V and max10?
Hi guys.
So I have a dedicated PLL chip that can phase lock an output clock of tens of Megahertz to an input clock of tens of Hertz, or million fold, using fractional N PLL. Simple dividers will cause too much jitter at these multiplications, and divide by N PLL are necessary. It's a great chip but I'm wondering if the same can be accomplished in an FPGA such as the Cyclone V or Max10 with the new Mega_Wizard. Let's say I want to phase lock a PPL output clock at 50MHz. to an input clock of 50Hz. - it looks like this kind of performance may be possible based on the information here: https://www.altera.com/products/fpga/features/stxv-fpll.html , but i'm not sure. Thank for your help. Cheers, Bob16 Replies
Altera_ForumHi,
Cyclone V supports PLL input clock range of 5MHz to 670MHz. https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf Max10 V supports PLL input clock range of 5MHz to 470MHz. https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_datasheet.pdf Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)- Altera_Forum
Hi Anard. Thanks for your reply.
So I guess that means I would have to build the rest of this 50Hz. to 50MHz. PLL myself, on the FPGA, from logic. I'm assuming this is possible as I have a chip that can do it. Should this be possible with ALtera FPGA and tools. Thanks for your help. Cheers, Bob - Altera_Forum
Hi,
Yes you can have your own logic for your design. Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) - Altera_Forum
Thanks, Anard.
- Altera_Forum
It will take more than logic to build your 50Hz to 50Mhz PLL. Not achievable within an FPGA IMHO.
- Altera_Forum
Thanks, gj_leeson.
- Altera_Forum
Hi,
For all FPGA PLLs/DCMs, there are a set of input/output frequencies defined. The PLLs can accept clocks within this frequency range and generate outputs also within the specified range. I'm not sure if they work in the Hz range though. Most of them work in the MHz ranges (5MHz to 550MHz). So, if you have a 50Hz clock on the board, you may need to use an external PLL of some sort that can work with the range you want. - Altera_Forum
Thanks eapenabrm. I have a dedicated chip for this function, and had hoped i could construct the same or similar logic in Cyclone or Max with or without some external components.
- Altera_Forum
PLLs are largely analogue, not digital. You cannot build a PLL out of digital logic alone, which means you can't build one on an FPGA.
- Altera_Forum--- Quote Start --- PLLs are largely analogue, not digital. You cannot build a PLL out of digital logic alone, which means you can't build one on an FPGA. --- Quote End --- Thanks, TCWORLD. I thought so. I imagine a solution would require interfacing through FPGA I/O to external circuit for analog elements - i think i've read about such circuits that take advantage of FPGA logic with an external circuit component to the function. This is the idea i have in mind. For the sake of example, lets say i am able to connect an external circuit to Max10 I/O pins to create an 'inboard/outboard' PLL for the Max to access, thereby minimizing outside world and possibly lowering noise. I haven't had a lot of experience with FPGA but this seems like a good idea. does this make sense? I'm pondering whether i could even build a fractional N function into this 'inboard/outboard' PLL...
