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Honored Contributor
Honored ContributorFractional N PLL implimentation in IP possible on Cyclone V and max10?
Hi guys. So I have a dedicated PLL chip that can phase lock an output clock of tens of Megahertz to an input clock of tens of Hertz, or million fold, using fractional N PLL. Simple divider...
Altera_ForumHonored Contributor
Honored ContributorHi,
For all FPGA PLLs/DCMs, there are a set of input/output frequencies defined. The PLLs can accept clocks within this frequency range and generate outputs also within the specified range. I'm not sure if they work in the Hz range though. Most of them work in the MHz ranges (5MHz to 550MHz). So, if you have a 50Hz clock on the board, you may need to use an external PLL of some sort that can work with the range you want.
