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Altera_Forum
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8 years ago

Fractional N PLL implimentation in IP possible on Cyclone V and max10?

Hi guys. So I have a dedicated PLL chip that can phase lock an output clock of tens of Megahertz to an input clock of tens of Hertz, or million fold, using fractional N PLL. Simple divider...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Thanks eapenabrm. I have a dedicated chip for this function, and had hoped i could construct the same or similar logic in Cyclone or Max with or without some external components.