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Altera_Forum
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8 years ago

Fractional N PLL implimentation in IP possible on Cyclone V and max10?

Hi guys. So I have a dedicated PLL chip that can phase lock an output clock of tens of Megahertz to an input clock of tens of Hertz, or million fold, using fractional N PLL. Simple divider...
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Altera_Forum
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8 years ago

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PLLs are largely analogue, not digital. You cannot build a PLL out of digital logic alone, which means you can't build one on an FPGA.

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Thanks, TCWORLD. I thought so.

I imagine a solution would require interfacing through FPGA I/O to external circuit for analog elements - i think i've read about such circuits that take advantage of FPGA logic with an external circuit component to the function. This is the idea i have in mind.

For the sake of example, lets say i am able to connect an external circuit to Max10 I/O pins to create an 'inboard/outboard' PLL for the Max to access, thereby minimizing outside world and possibly lowering noise. I haven't had a lot of experience with FPGA but this seems like a good idea. does this make sense? I'm pondering whether i could even build a fractional N function into this 'inboard/outboard' PLL...