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Altera_Forum
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8 years ago

Fractional N PLL implimentation in IP possible on Cyclone V and max10?

Hi guys. So I have a dedicated PLL chip that can phase lock an output clock of tens of Megahertz to an input clock of tens of Hertz, or million fold, using fractional N PLL. Simple divider...
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Altera_Forum
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8 years ago

Hi Anard. Thanks for your reply.

So I guess that means I would have to build the rest of this 50Hz. to 50MHz. PLL myself, on the FPGA, from logic.

I'm assuming this is possible as I have a chip that can do it. Should this be possible with ALtera FPGA and tools. Thanks for your help.

Cheers,

Bob