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Honored Contributor
Honored ContributorFractional N PLL implimentation in IP possible on Cyclone V and max10?
Hi guys. So I have a dedicated PLL chip that can phase lock an output clock of tens of Megahertz to an input clock of tens of Hertz, or million fold, using fractional N PLL. Simple divider...
Altera_ForumHonored Contributor
Honored ContributorIt will take more than logic to build your 50Hz to 50Mhz PLL. Not achievable within an FPGA IMHO.
