Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Fractional N PLL implimentation in IP possible on Cyclone V and max10?

Hi guys. So I have a dedicated PLL chip that can phase lock an output clock of tens of Megahertz to an input clock of tens of Hertz, or million fold, using fractional N PLL. Simple divider...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

Cyclone V supports PLL input clock range of 5MHz to 670MHz.

https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf

Max10 V supports PLL input clock range of 5MHz to 470MHz.

https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_datasheet.pdf

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)