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Altera_Forum
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8 years ago

Fractional N PLL implimentation in IP possible on Cyclone V and max10?

Hi guys. So I have a dedicated PLL chip that can phase lock an output clock of tens of Megahertz to an input clock of tens of Hertz, or million fold, using fractional N PLL. Simple divider...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

Yes you can have your own logic for your design.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)