FPGA screen problem; Time requirements not meet

Question

Hi everybody, I read the similar subject here but I didn't find the solution of my problem.

I have an image processing project, I'm sure that there isn't any error in algorithm and files which I added to project. But when I loaded .sof file to Cyclone II, it's written there is no signal at the screen. what can be the reason of this problem?

When I compiled project, there isn't any error but there is Critical Warning: Time Requirements not Met. I think maybe problem is sourced from this warning and I have to add .sdc file.. what do you think about this?

please help me.. thank you.

altera_forum · Answer

I have met this problem many time.

my advice is that , create .sdc file as the warning says.

once you create and compile your project.

timequest tells you where is the problem ( which occurs slacks ).

you may need to correct those point ( buffering, dividing and so on ).

make sure of those.

1. did you create .sdc file?

2. did you add .sdc on your *.qsf file?

3. do you know how to see report?

4. do you know how to correct the logic?

tell me those.

I may find solution step by step.

I know this problem is too hard to understand.

you get bad picture when you just add one register or signaltapII( almost nothing ), even you got good picture once.

I thought it was some kind of bug in QuartusII.

in fact, this is not QuartusII's problem.

as long as this is not bug of your tool, there is way to fix it!

altera_forum · Answer

Thank you for reply, ok let us find solution step by step;

First of all, after your message I try to learn creating .sdc file. I read the the document about this subject here (at the page 11, TASK 4 ) >> http://www.tech.mtu.edu/nsfate/workshop%20labs/lab%201%20-%20introduction%20to%20quartus.pdf

In this document, it is written that 'Enable multicorner timing analysis during compilation' , but I didn't find this part in Quartus version 12.

Then I skipped this step and continued with 'Create a Timing Netlist' . I made this. But after that there is another step says 'select all of the input and sel names'. I didn't understand this part. If you answered about these, then I will continue to ask another step.

altera_forum · Answer

Hi AKIRA ,

Thank you for reply; after your message I try to learn creating .sdc file.

In the document I read about this subject, it says use the 'Time Analysis Setting' and 'Enable multicorner timing analysis during compilation' but I didn't find this choose in Quartus version 12.

So if you answer this part, then we will continue step by step.

altera_forum · Answer

If its a timing failure, Im not surprised it doesnt work.

Load the timing report and look at the failing paths. Then re-write the source code to improve the timing between registers.

And dont post the same question multiple times!

altera_forum · Answer

Apart from the relevance of timing failure, I wonder what "no signal at the screen" means. I guess, it's not only a timing problem.

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FPGA screen problem; Time requirements not meet

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