FPGA screen problem; Time requirements not meet

I have met this problem many time.

my advice is that , create .sdc file as the warning says.

once you create and compile your project.

timequest tells you where is the problem ( which occurs slacks ).

you may need to correct those point ( buffering, dividing and so on ).

make sure of those.

1. did you create .sdc file?

2. did you add .sdc on your *.qsf file?

3. do you know how to see report?

4. do you know how to correct the logic?

tell me those.

I may find solution step by step.

I know this problem is too hard to understand.

you get bad picture when you just add one register or signaltapII( almost nothing ), even you got good picture once.

I thought it was some kind of bug in QuartusII.

in fact, this is not QuartusII's problem.

as long as this is not bug of your tool, there is way to fix it!