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Altera_Forum's avatar
Altera_Forum
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12 years ago

FPGA screen problem; Time requirements not meet

Hi everybody, I read the similar subject here but I didn't find the solution of my problem. I have an image processing project, I'm sure that there isn't any error in algorithm and files which ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Apart from the relevance of timing failure, I wonder what "no signal at the screen" means. I guess, it's not only a timing problem.