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Altera_Forum
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13 years ago

FPGA screen problem; Time requirements not meet

Hi everybody, I read the similar subject here but I didn't find the solution of my problem. I have an image processing project, I'm sure that there isn't any error in algorithm and files which ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi AKIRA ,

Thank you for reply; after your message I try to learn creating .sdc file.

In the document I read about this subject, it says use the 'Time Analysis Setting' and 'Enable multicorner timing analysis during compilation' but I didn't find this choose in Quartus version 12.

So if you answer this part, then we will continue step by step.