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Altera_Forum
Honored Contributor
Honored ContributorFPGA screen problem; Time requirements not meet
Hi everybody, I read the similar subject here but I didn't find the solution of my problem. I have an image processing project, I'm sure that there isn't any error in algorithm and files which ...
Altera_ForumHonored Contributor
Honored ContributorIf its a timing failure, Im not surprised it doesnt work.
Load the timing report and look at the failing paths. Then re-write the source code to improve the timing between registers. And dont post the same question multiple times!
