FPGA screen problem; Time requirements not meet

Thank you for reply, ok let us find solution step by step;

First of all, after your message I try to learn creating .sdc file. I read the the document about this subject here (at the page 11, TASK 4 ) >> http://www.tech.mtu.edu/nsfate/workshop%20labs/lab%201%20-%20introduction%20to%20quartus.pdf

In this document, it is written that 'Enable multicorner timing analysis during compilation' , but I didn't find this part in Quartus version 12.

Then I skipped this step and continued with 'Create a Timing Netlist' . I made this. But after that there is another step says 'select all of the input and sel names'. I didn't understand this part. If you answered about these, then I will continue to ask another step.