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Altera_Forum's avatar
Altera_Forum
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13 years ago

FPGA screen problem; Time requirements not meet

Hi everybody, I read the similar subject here but I didn't find the solution of my problem. I have an image processing project, I'm sure that there isn't any error in algorithm and files which ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

FvM gave me good hint.

so, how do you know your signal is right?

one another question.

did you do simulation?