FPGA Configuration problem using Flash Memory

Is this a custom board?

What configuration scheme are you using?

Are your MSEL pins set accordingly?

Are your pin assignments all correct for the MAX device?

Are you able to program the FPGA via JTAG?

Jake

Hi Jake, Thanx

here are the answers for your questions:-

1) My board is Stratix II GX PCIe development kit.

2) I have tried with both PS and FPP schemes.

3) Please explain on MSEL pins and how to actually set them....

4) Whatever signals I have got in Parallel Flash Loader megafunction, I have just mapped those to the MAX device.

They may be correct otherwise howcome the Flash is getting programmed!

5) Yes I am able to program the FPGA through JTAG.

Also, I have a bit confusion while setting the "Option Bit" address, while generating the PFL megacore and setting the address while converting design sof to flash pof. What actually is the relation between the two addresses?

-Amit

If I recall correctly, the flash loader that comes in the MAX device has a dependency on one of the push buttons. I think you have to press switch S1 to allow the flash programmer to continue on to program the part. It's been a while, but I don't think the flash loader will even detect that there's a part out there unless the button is pushed.

One other thing I recall about digging through this: The documentation wasn't very clear about this push-button.

Please refer to the user manual for your board ...

http://www.altera.com/literature/manual/mnl-s2gx-pci-express-devkit.pdf

The MSEL pins determine the configuration mode for the FPGA. Table 2-7 in the user manual details the option for your board. You have to set the pins correctly for it to work. In addition, your board has Mode DIP switches and the RUnLU switch. These must be set accordingly.

When I asked if your MAX pin assignments were correct I also meant the configuration pins to the FPGA. Doesn't do much good to be able to load the flash if you can't talk to the FPGA. Table 2-10 in the manual details the required signals.

Jake

--- Quote Start ---

If I recall correctly, the flash loader that comes in the MAX device has a dependency on one of the push buttons. I think you have to press switch S1 to allow the flash programmer to continue on to program the part. It's been a while, but I don't think the flash loader will even detect that there's a part out there unless the button is pushed.

One other thing I recall about digging through this: The documentation wasn't very clear about this push-button.

--- Quote End ---

A bit more info on this...

If you try to auto-detect the JTAG chain from the Quartus programmer and you get this message:

Info: Device 1 silicon ID is not ready - waiting for pfl_flash_access_granted to be asserted

the Parallel Flash Loader in the MAX II device is witholding access to the flash. It will eventually time-out with an error message:

Error: Failed to get access to the flash interface

If you press button S1 before the time-out, your auto-detect will come back with the MAX II 570, a 512 MB CFI Flash and the 2SGX90. You should now be able to communicate with the PFL and start programming.

I couldn't find anything in the board's reference manual that discussed this, but there's a note in the readme.txt file that get put in teh docs directory when you install the CD that came with the kit.

Hi Jake,

following are the signals which i have mapped to the MAXII device:

fpga_conf_done,

fpga_nstatus,

fpga_pgm,

pfl_clk,

pfl_flash_access_granted, (always pulled to high)

pfl_nreset, (always pulled to high)

flash_addr,

flash_data,

flash_nce,

flash_noe,

flash_nwe,

fpga_data,

fpga_dclk,

fpga_nconfig,

pfl_flash_access_request (high)

and the settings for the S6 dip switch are:

CONFIG_MODE0 - low

CONFIG_MODE1 - low

DIPSW_PGM0 - high (if i am connecting fpga_pgm pins to dip

switch pgm pins of the max device)

DIPSW_PGM1 - low

DIPSW_PGM2 - low

VCCHTX_ADJ - low

RUnLU - high

HSMCA_JTAG - high

HSMCB_JTAG - high

CLK_SEL - high

thanx

-Amit

Hi all,

I have a similar problem, however, not exactly the same. I'm also using the Stratix II GX PCIe development board, and I'm trying to generate the flash image, which could be loaded into the flash device. Since I want to preserve the factory default firmware, I thought it would be nice to load my firmware in one of the available pages. I presume the generation of such an image involves the usage of Convert Programming Files tool. Right ?

However, as gargamit mentioned, it is not clear how to set up correclty the "Option bit" address. I think the page addresses should be set to those values mentioned in the Reference Manual.

i'm back with some new findings ...

looking into the firmware of the configuration controller (PFL), I found this comment:

//+-----------------------------------------

//| Parallel Flash Loader (PFL) Megafunction

//|

//| Flash Size: 512Mb CFI (Spansion)

//| Flash Data Width: 16 bits

//| Option Bits Addr: 0x1FF.0000

//| Clock Speed: 100MHz

//| Retry on Error: Same Page

So, it seems that option bits address should be 0x1ff0000. However, in the reference manual (Table 2-8, page 2-16) the PFL option bits are at 0x3fffff0. I'm really confused. :confused:

By the way, the flash image (pof) that I create with Quartus II v8.0 SP1, is not accepted by the programmer, because the PFL version of board configuration controller is v2, instead of the expected v3. :eek:

wrap up ...

I created the new PFL instance (pfl3_top.v) using Quartus II v8.0 MegaWizard Plug-in manager. I kept the Option bits Address pointing to the same location as before, i.e. 0x1ff0000 (not the one mentioned in the reference manual). Recompiled the project, and loaded the new firmware into the on-board MAX II device. To verify that I did not mess up the board, I tried the factory default config, which was successfully loaded by the new controller.

Then I generated a new flash image using the Convert Programming Files utility. I added two pages, page_0 and page_1, holding the factory default SOF, and my test firmware, respectively. I set the Option bits Address to the above mentioned 0x1ff0000. In the programmer, using the POF that I generated in the previous step, I have the possibility to program the selected pages of the flash device. Note, that you may have to update the OPTION BITS to refresh the pointers. It apears in the list of programmable pages (in my case, the list contains page_0, page_1 and OPTION BITS).

For reference, here is the content of the memory map file:

-------------------------------------------------------

BLOCK START ADDRESS END ADDRESS

Page_0 0x00000000 0x00316467

Page_1 0x00400000 0x00716467

OPTION BITS 0x01FF0000 0x01FF0080

-------------------------------------------------------

I hope it helps.

my design file is a simple led glow project. I am making a .pof of it with option bits as mentioned by u ie is 0x1ff0000. and adding my design to page_0 with the block settings u have mentioned.

I have created a pfl for it too using 7.2v of quartus,with option bits as 0x1ff0000. my settings for s6 (dip switch of stratix2gx pcie development board) are :"0000001111".

when i dump the code into the flash using the pfl , It shows "successfully performed operation", but i see no led glowing .

Even when i press the s1 switch to configure the fpga ,i see no response :confused: :confused: . kindly help me ... If my procedure is wrong then let me know ...