FPGA Configuration problem using Flash Memory

Hi Jake,

following are the signals which i have mapped to the MAXII device:

fpga_conf_done,

fpga_nstatus,

fpga_pgm,

pfl_clk,

pfl_flash_access_granted, (always pulled to high)

pfl_nreset, (always pulled to high)

flash_addr,

flash_data,

flash_nce,

flash_noe,

flash_nwe,

fpga_data,

fpga_dclk,

fpga_nconfig,

pfl_flash_access_request (high)

and the settings for the S6 dip switch are:

CONFIG_MODE0 - low

CONFIG_MODE1 - low

DIPSW_PGM0 - high (if i am connecting fpga_pgm pins to dip

switch pgm pins of the max device)

DIPSW_PGM1 - low

DIPSW_PGM2 - low

VCCHTX_ADJ - low

RUnLU - high

HSMCA_JTAG - high

HSMCB_JTAG - high

CLK_SEL - high

thanx

-Amit