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Altera_Forum's avatar
Altera_Forum
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12 years ago

FIR Compiler and FIR feedback filter.

Hello guys,

Today I'm trying implementing a FIR feedback in my design with the FIR compiler megafunction.

I've created 25 8-bit coefficients and imported them in the FIR compiler tool.

The coefficient as something similar to these ones (but mine are always positive):

http://www.mathworks.com/help/releases/R2013b/signal/ref/prony_ex1.png

Due to the feedback implementation I need that the output of the filter at time 'k' act on the input at k+1. So I need one period delay bettwen input and output.

http://www.originlab.com/www/helponline/origin/en/images/Algorithm_(IIR_Filters)/IIR_Filter_1.png

In FIR-Compiler I choose the 'fully parallel structure' option as it is supposed processing every input every clock period and generating a new output every clock period.

After I have also created the simulation files needed to simulate the filter with modelsim. Simulating the filter shows that there are about 14 clocks period delays between input samples and output samples..

I'm a little confused... Do you have any suggestions ??

Thank you very much. have a nice day.

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  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    so it is clock latency(pipe). the fir compiler may tell you the latency through your design.

    you can readily code by hand without any registers if speed allows.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I don't believe that FIR compiler is designed for applications like yours (with minimal delay). But you didn't tell the implementation details so we can't check the results.

    It isn't however too complicated to write a minimal delay FIR implementation from the scratch. 1 multiplier and 1 adder makes the shortest signal path, how many pipeline levels you place is up to you, respectively the speed requirements.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thank you guys,

    What do you mean by "implementation details" ? I have a 25 FIR taps. I have simulated the whole system with another software using the classic serial structure:

    http://upload.wikimedia.org/wikipedia/commons/9/95/Fir_filter_df1.png

    By the way in an FPGA this structure will introduce a something like 16 delays before I can get the output (clock through whole dffs). Because I'm going at 75 MHz and I have a system clock of 150 i can speed up the system at a maximum value of 2 which is not enough.

    So I have seen that the parallel structure process 1 input and 1 output in 1 clock period (so FIR compiler told me..) by the way it was not specified that there was latency to take into account. I need a FIR with 25 taps that have a 1 clock latency and 1 clock output processing..

    It seems I am in a "cul-de-sac"..
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    try set FIR to transposed structure. you may then get less delay as delay stages could be used as pipeline registers between adders.

    delay in parallel structure is caused by the addition ladder
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    What do you mean by "implementation details" ?

    --- Quote End ---

    Simply all setting in the FIR compiler. But as already mentioned, the FIR compiler is probably not prepared to generate a minimal delay structure.

    --- Quote Start ---

    try set FIR to transposed structure.

    --- Quote End ---

    Yes, that's what I mean. In the transposed structure, the adder pipeline delay makes the FIR delay line.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thank you guys.. I'm very busy these days..

    The FIR compiler can be implemented as:

    - Fully serial Filter -> 1 input every 16 clocks and 1 output every 16 clocks -> Not suitable.

    - Multi bit Serial Filter -> 1 input every 8 clocks and 1 output every 8 clocks -> Not suitable.

    - Fully parallel Filter -> 1 input every 1 clock, 1 output every 1 clock -> Ok but registers delay makes it not suitable

    - Multy-Cycle -> 1 input every 2 clocks periods and 1 output every 2 clocks period -> It would be ok because I can speedup by a 2 factor. By the way the pipeline makes it not suitable too..

    I could put it down by hand but the filter taps could be much more and it would be sooooo tedious.....

    I will try with few coefficients for now.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I have the impression that you are designing IIR filter using two FIRs(forward and feedback). Sounds good idea if it tolerates the delay. You might well see your math model if it tolerates delay and how far.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    The transposed stucture model seems to work fine.

    Thank you guys ! I really appreciate.