Forum Discussion
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- What do you mean by "implementation details" ? --- Quote End --- Simply all setting in the FIR compiler. But as already mentioned, the FIR compiler is probably not prepared to generate a minimal delay structure. --- Quote Start --- try set FIR to transposed structure. --- Quote End --- Yes, that's what I mean. In the transposed structure, the adder pipeline delay makes the FIR delay line.