Forum Discussion
Altera_Forum
Honored Contributor
12 years agoI don't believe that FIR compiler is designed for applications like yours (with minimal delay). But you didn't tell the implementation details so we can't check the results.
It isn't however too complicated to write a minimal delay FIR implementation from the scratch. 1 multiplier and 1 adder makes the shortest signal path, how many pipeline levels you place is up to you, respectively the speed requirements.