Honored Contributor
Honored ContributorThank you guys,
What do you mean by "implementation details" ? I have a 25 FIR taps. I have simulated the whole system with another software using the classic serial structure: http://upload.wikimedia.org/wikipedia/commons/9/95/Fir_filter_df1.png By the way in an FPGA this structure will introduce a something like 16 delays before I can get the output (clock through whole dffs). Because I'm going at 75 MHz and I have a system clock of 150 i can speed up the system at a maximum value of 2 which is not enough. So I have seen that the parallel structure process 1 input and 1 output in 1 clock period (so FIR compiler told me..) by the way it was not specified that there was latency to take into account. I need a FIR with 25 taps that have a 1 clock latency and 1 clock output processing.. It seems I am in a "cul-de-sac"..
