Honored Contributor
Honored ContributorThank you guys.. I'm very busy these days..
The FIR compiler can be implemented as: - Fully serial Filter -> 1 input every 16 clocks and 1 output every 16 clocks -> Not suitable. - Multi bit Serial Filter -> 1 input every 8 clocks and 1 output every 8 clocks -> Not suitable. - Fully parallel Filter -> 1 input every 1 clock, 1 output every 1 clock -> Ok but registers delay makes it not suitable - Multy-Cycle -> 1 input every 2 clocks periods and 1 output every 2 clocks period -> It would be ok because I can speedup by a 2 factor. By the way the pipeline makes it not suitable too.. I could put it down by hand but the filter taps could be much more and it would be sooooo tedious..... I will try with few coefficients for now.
