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Altera_Forum's avatar
Altera_Forum
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12 years ago

FIR Compiler and FIR feedback filter.

Hello guys,

Today I'm trying implementing a FIR feedback in my design with the FIR compiler megafunction.

I've created 25 8-bit coefficients and imported them in the FIR compiler tool.

The coefficient as something similar to these ones (but mine are always positive):

http://www.mathworks.com/help/releases/R2013b/signal/ref/prony_ex1.png

Due to the feedback implementation I need that the output of the filter at time 'k' act on the input at k+1. So I need one period delay bettwen input and output.

http://www.originlab.com/www/helponline/origin/en/images/Algorithm_(IIR_Filters)/IIR_Filter_1.png

In FIR-Compiler I choose the 'fully parallel structure' option as it is supposed processing every input every clock period and generating a new output every clock period.

After I have also created the simulation files needed to simulate the filter with modelsim. Simulating the filter shows that there are about 14 clocks period delays between input samples and output samples..

I'm a little confused... Do you have any suggestions ??

Thank you very much. have a nice day.

18 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    you will get delay inside filter(group delay) on top of usual latency as signal builds up.

    group delay = 1/2 of filter order (if fir is symmetric)
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    you will get delay inside filter(group delay) on top of usual latency as signal builds up.

    group delay = 1/2 of filter order

    --- Quote End ---

    Thank you kaz !

    Probably i was not clear enaugh. My filter is 1-causal. So I don't have to wait the signal to reach the maximum at (n-1)/2. I have only the causal part (eg: only the right half of a gaussian).

    The impulse response is like

    [0 10 9 8 7 6 5 4 3 2 1 0]

    So if my input at k-1 is 10 I expect to have 10 at time k at the output of the filter. But this does not happen and I can't understand why..
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    x = [10 0 0 0 0 0 0 0 0 0 0];

    h = [0 10 9 8 7 6 5 4 3 2 1 0];

    y = filter(h,1,x);

    y =

    0 100 90 80 70 60 50 40 30 20 10

    I hope this helps
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thank you kaz

    It is what I was supposed to get running modelsim.. I will take a screenshot as soon as I can
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    It will help if you tell us how do you measure your delay.

    --- Quote End ---

    So, this is the filter structure:

    https://www.alteraforum.com/forum/attachment.php?attachmentid=8514

    And this is the modelsim output:

    https://www.alteraforum.com/forum/attachment.php?attachmentid=8515

    The first signal is the input signal, then there is the output and finally the clock. As you see there is a delay between input and output greater than one. I can't really understand why..
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    you mean delay from first nonzero input to 1st nonzero output is so many cycles. This must be clock latency through your filter. check your pipeline settings if any.

    additionally you need to check your scaling effect on output
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    you mean delay from first nonzero input to 1st nonzero output is so many cycles. This must be clock latency through your filter. check your pipeline settings if any.

    --- Quote End ---

    I have a pipelineLevel equals to 1. I've tried to put it to 0. Effectively the delay decreases but remains higher than one period (about ten period).. So it is not possible to use the ouput on the input at the right time...

    I can try with the full symmetric structure but as I enter the filter at 75 MHz and my maximum clock rate is 150 MHz I'cant comply with the delays needed by the filter to process the input and the output (16 clocks for 1 input and 1 output).
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    try value of 10 only followed by zeros as above example then check how many zeros you get at output before 100 comes out. This way you rule out any scaling effect causing zeros at output. normally filters need registers at each mult and adders but for slow speeds one register might be enough

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    try value of 10 only followed by zeros as above example then check how many zeros you get at output before 100 comes out. This way you rule out any scaling effect causing zeros at output. normally filters need registers at each mult and adders but for slow speeds one register might be enough

    --- Quote End ---

    So this is my output with only a 10 valued input:

    https://www.alteraforum.com/forum/attachment.php?attachmentid=8516

    It seems it leads to the same problem..