--- Quote Start ---
you mean delay from first nonzero input to 1st nonzero output is so many cycles. This must be clock latency through your filter. check your pipeline settings if any.
--- Quote End ---
I have a pipelineLevel equals to 1. I've tried to put it to 0. Effectively the delay decreases but remains higher than one period (about ten period).. So it is not possible to use the ouput on the input at the right time...
I can try with the full symmetric structure but as I enter the filter at 75 MHz and my maximum clock rate is 150 MHz I'cant comply with the delays needed by the filter to process the input and the output (16 clocks for 1 input and 1 output).
Honored Contributor
