Facing problems in constraining Negative Setup Slack

Hello all,

I am facing problems in constraining Negative Slacks (for a 50Mhz clock and 150MhZ clock both generated clocks). I had a negative slack of -59 which was because of using a 44_24 LPM divider which I solved using 2 stages of pipeline. There were few other slack issues which I constrained using set_clock_groups and a set_false_path.

Now, I have setup negative slack of -14 and -6 (two different generated clocks) within a module where the input to the module comes from a written register(in SW), using which a division is performed and the value is stored in a register. The same happens with one more module. I am not sure why lot of timing issues come up with Division (Be it using lpm or a simple arithemtic division).

I am quite new to Timing analysis, that I am not sure if I should alter the code which can solve the timing issues or use constraints set_false_path / multicycle paths / setting max delays to ignore the timing analysis. I dont want to alter the code much which has been already tested.

I am attaching the Setup Timing Closure Report, the Source code of the module and the SDC File.

Looking forward to your suggestions! Thank you.