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Altera_Forum
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10 years ago

Facing problems in constraining Negative Setup Slack

Hello all, I am facing problems in constraining Negative Slacks (for a 50Mhz clock and 150MhZ clock both generated clocks). I had a negative slack of -59 which was because of using a 44_24 LPM ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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If you have a timing problem you can solve it editing design files or if violation is small (ex. 0.5 ns) changing optimization parameters or trying design space exploration (multiple compile seed).

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Yes, I have tried optimizing using the Timing optimization advisor. It has not helped much. I still get a lot of unconstrained paths with a high negative setup slack. I dont have a DSE to perform Design Space Exploration.