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If slack is high you have to lower your frequency or add pipeline stages into your design.. no way to escape.. 150 MHz is an high frequency for an FPGA and circuit need to be carefully designed.
DSE is included into Quartus installation but can't solve 14ns violation..
Division is very slow.. maybe you need more latency?
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Yes. I made the division faster by changing the logic. The setup slack for the System Clock (50MHz) is fine now. But the one with 150MHz is still lagging. Could you please look into the source code and let me know if Im missing something. The Timing report for it is also in the attachments. Thanks a lot!
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