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Honored Contributor
Honored ContributorFacing problems in constraining Negative Setup Slack
Hello all, I am facing problems in constraining Negative Slacks (for a 50Mhz clock and 150MhZ clock both generated clocks). I had a negative slack of -59 which was because of using a 44_24 LPM ...
Altera_ForumHonored Contributor
Honored ContributorIf you want to change latency of divider IP you need to change your design.. also if you insert registers between path you have to edit your design.. there is no simply way to solve it.
With SDC you can ignore timing failure but just ignore (false_path command).. then your design may not works. Also multicycle.. is like ignoring if your design don't consider it.
