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Honored Contributor
Honored ContributorFacing problems in constraining Negative Setup Slack
Hello all, I am facing problems in constraining Negative Slacks (for a 50Mhz clock and 150MhZ clock both generated clocks). I had a negative slack of -59 which was because of using a 44_24 LPM ...
Altera_ForumHonored Contributor
Honored ContributorIf slack is high you have to lower your frequency or add pipeline stages into your design.. no way to escape.. 150 MHz is an high frequency for an FPGA and circuit need to be carefully designed.
DSE is included into Quartus installation but can't solve 14ns violation.. Division is very slow.. maybe you need more latency?
