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Altera_Forum
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10 years ago

Facing problems in constraining Negative Setup Slack

Hello all, I am facing problems in constraining Negative Slacks (for a 50Mhz clock and 150MhZ clock both generated clocks). I had a negative slack of -59 which was because of using a 44_24 LPM ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

If slack is high you have to lower your frequency or add pipeline stages into your design.. no way to escape.. 150 MHz is an high frequency for an FPGA and circuit need to be carefully designed.

DSE is included into Quartus installation but can't solve 14ns violation..

Division is very slow.. maybe you need more latency?