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It is need entire project because timing depend on a lot of things (device, pinout, etc..) but I don't think I have enough time to do your project analysis now. Use Timequest to find what path are failing and then edit design..
You use C8 device.. maybe you can upgrade to a faster speed grade?
Another way is to change phase shift to improve setup times..
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Thanks a lot! Will try it. But will setting up a lateny be helpful here?
-6.109(Setup slack) ; APP-FPGA_Application_Logic:inst1|FilCtrl:inst30|PWM_Gen:inst1|\PWMControl:v_pulse_count_nom[0] ; APP-FPGA_Application_Logic:inst1|FilCtrl:inst30|PWM_Gen:inst1|\PWMControl:v_updatePWMvalue ; 150Mhz_Osc_Clock ; 150Mhz_Osc_Clock ; 6.666 ; 0.369 ; 13.145 ;
Is setting up a latency for the specific target a good idea? Will it help? If it is, what is the SDC command to set up latency for the specific target? I tried with different Tcl commands to specify target but didnt work.
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