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Altera_Forum's avatar
Altera_Forum
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14 years ago

error in dual edge dff in vhdl

Some where in web I found a dual edge DFF in vhdl and add to my cyclone iii project, after compiling there comes a strange error message :

Error (10327): VHDL error at fdff.vhd(20): can't determine definition of operator ""="" -- found 0 possible definitions

and my codes are :

library IEEE ;

use IEEE.STD_LOGIC_1164.ALL,IEEE.Numeric_std.ALL;

entity edff is

generic (

impl_rn : integer := 1 ;

impl_sn : integer := 1 ) ;

port (

rn : in std_ulogic ;

sn : in std_ulogic ;

d : in std_ulogic ;

c : in std_ulogic ;

q : out std_ulogic ) ;

end edff ;

architecture behavior of edff is

signal ff_rise , ff_fall : std_ulogic ;

begin

process ( rn , sn , c )

begin

if ( impl_rn = 1 and rn = 0 ) then

ff_rise <= 0;

elsif ( impl_sn = 1 and sn = 0 ) then

ff_rise <= 1;

elsif rising_edge ( c ) then

if ( d = 1 ) then

ff_rise <= not( ff_fall ) ;

else ff_rise <= ff_fall ;

end if ;

end if ;

end process ;

process ( rn , sn , c )

begin

if ( implrn =1 AND rn = 0 ) then

ff_fall <= 0;

elsif ( implsn =1 AND sn = 0 ) then

ff_fall <= 0;

elsif falling_edge ( c ) then

if ( d = 1 ) then

ff_fall <= not( ff_rise ) ;

else ff_fall <= ff_rise ;

end if ;

end if ;

end process ;

q <= 0 when ( implrn =1 AND rn = 0 ) else

1 when ( impl_sn =1 AND sn = 0 ) else

ff_ris XOR ff_fall ;

end behavior ;

Can someones help me solve this problem ???

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    first of all, dual edge flip flops are not suitable for FPGA designs. I recommend you just double the clock rate and do it that way instead.

    Secondly, you need to compare std_ulogics to '0' or '1', not 0 or 1. 0 is an integer, '0' is one of std_ulogic's enumerated types.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The input clock is from 1Hz to 125M Hz , without using FPGA I cannot find other suitable IC do the job !!

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    FPGA will be fine, when you understand what you are doing. Would this clock vary or be constant? why cant you use a PLL just to multiply the clock by 2? that way you can use a toggle bit to detect the two different "edges".

    What are you actually trying to do?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    for Megafunction using PLL , i have to enter the input clock value , but my input clock is vary from 1Hz to 125MHz , is it possible input a "false" input value said 50M to PLL but the actual value is from 1Hz to 125MHz so that a 2Hz to 250 MHz output from PLL ??? Can I use other method rather than PLL ??

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    why does the input clock vary? That is generally not a good idea for an FPGA. Best to have a system clock and then get the data from the input clock into the system clock domain.

    And I know 1Hz is not suitable for a PLL. I think there is a minimum of 1MHz or something.

    Please explain where this clock comes from. If it varies like you say, then its not really a clock.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    When you fix the various typos and missing quotes for binary constants, the design can compile in Quartus. I suggest, that you'll try it and find out yourself, which problems are involved with it.

    As an additional issue, newer FPGA families don't have asynchronous set for FFs. So Quartus must implement additional latches to emulate the set/reset function for ff_rise. You should decide, if it's actually needed for your design.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks all of your replies , I upload part of my quartus design file which is used for 8 inputs channels from two AD9481 in interleaving mode ( used for DSO ) . Two PLL generates two 100M , max 125M clock ( 180 phase difference from each other ) feed to two CLK_MODULE , which is a clock divider , from the value of SEL [4:0] , so 1Hz to 100M Hz is generated out of MEM_CLK_OUT and 2.5MHz to 125MHz is generated out of ADC_CLK_OUT ( to AD9481) . Both of MEM_CLK_OUT are input to one clk input of module MEM_CONTROL_H , for some reasons only one input can be used as I cannot find way to modify it . The function of CLK input of MEM_CONTROL_H is on every raising edge of input CLK , ADC_CH1_DATA[ 7:0] and ADC_CH2_DATA [7:0] is put into two array of size 8192 . The problem is how can I combine two 180 phase difference clock to one input clock to MEM_CONTROL_H ????

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Altera FPGA have double data rate (DDR) in- and output registers to read or write data signals valid on both edges. No need to use dubious dual-edge clocked FFs.