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Honored Contributor
Honored Contributorerror in dual edge dff in vhdl
Some where in web I found a dual edge DFF in vhdl and add to my cyclone iii project, after compiling there comes a strange error message : Error (10327): VHDL error at fdff.vhd(20): can't dete...
Altera_ForumHonored Contributor
Honored Contributorwhy does the input clock vary? That is generally not a good idea for an FPGA. Best to have a system clock and then get the data from the input clock into the system clock domain.
And I know 1Hz is not suitable for a PLL. I think there is a minimum of 1MHz or something. Please explain where this clock comes from. If it varies like you say, then its not really a clock.
