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Honored Contributor
Honored Contributorerror in dual edge dff in vhdl
Some where in web I found a dual edge DFF in vhdl and add to my cyclone iii project, after compiling there comes a strange error message : Error (10327): VHDL error at fdff.vhd(20): can't dete...
Altera_ForumHonored Contributor
Honored Contributorfirst of all, dual edge flip flops are not suitable for FPGA designs. I recommend you just double the clock rate and do it that way instead.
Secondly, you need to compare std_ulogics to '0' or '1', not 0 or 1. 0 is an integer, '0' is one of std_ulogic's enumerated types.
