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Altera_Forum's avatar
Altera_Forum
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14 years ago

error in dual edge dff in vhdl

Some where in web I found a dual edge DFF in vhdl and add to my cyclone iii project, after compiling there comes a strange error message : Error (10327): VHDL error at fdff.vhd(20): can't dete...
Altera_Forum's avatar
Altera_Forum
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14 years ago

FPGA will be fine, when you understand what you are doing. Would this clock vary or be constant? why cant you use a PLL just to multiply the clock by 2? that way you can use a toggle bit to detect the two different "edges".

What are you actually trying to do?