Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

error in dual edge dff in vhdl

Some where in web I found a dual edge DFF in vhdl and add to my cyclone iii project, after compiling there comes a strange error message : Error (10327): VHDL error at fdff.vhd(20): can't dete...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

for Megafunction using PLL , i have to enter the input clock value , but my input clock is vary from 1Hz to 125MHz , is it possible input a "false" input value said 50M to PLL but the actual value is from 1Hz to 125MHz so that a 2Hz to 250 MHz output from PLL ??? Can I use other method rather than PLL ??