Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

error in dual edge dff in vhdl

Some where in web I found a dual edge DFF in vhdl and add to my cyclone iii project, after compiling there comes a strange error message : Error (10327): VHDL error at fdff.vhd(20): can't dete...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

When you fix the various typos and missing quotes for binary constants, the design can compile in Quartus. I suggest, that you'll try it and find out yourself, which problems are involved with it.

As an additional issue, newer FPGA families don't have asynchronous set for FFs. So Quartus must implement additional latches to emulate the set/reset function for ff_rise. You should decide, if it's actually needed for your design.