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Honored Contributor
Honored Contributorerror in dual edge dff in vhdl
Some where in web I found a dual edge DFF in vhdl and add to my cyclone iii project, after compiling there comes a strange error message : Error (10327): VHDL error at fdff.vhd(20): can't dete...
Altera_ForumHonored Contributor
Honored ContributorAltera FPGA have double data rate (DDR) in- and output registers to read or write data signals valid on both edges. No need to use dubious dual-edge clocked FFs.
