error in dual edge dff in vhdl

Thanks all of your replies , I upload part of my quartus design file which is used for 8 inputs channels from two AD9481 in interleaving mode ( used for DSO ) . Two PLL generates two 100M , max 125M clock ( 180 phase difference from each other ) feed to two CLK_MODULE , which is a clock divider , from the value of SEL [4:0] , so 1Hz to 100M Hz is generated out of MEM_CLK_OUT and 2.5MHz to 125MHz is generated out of ADC_CLK_OUT ( to AD9481) . Both of MEM_CLK_OUT are input to one clk input of module MEM_CONTROL_H , for some reasons only one input can be used as I cannot find way to modify it . The function of CLK input of MEM_CONTROL_H is on every raising edge of input CLK , ADC_CH1_DATA[ 7:0] and ADC_CH2_DATA [7:0] is put into two array of size 8192 . The problem is how can I combine two 180 phase difference clock to one input clock to MEM_CONTROL_H ????