Error: Can't synthesize current design -- Top partition does not contain any logic

Looks to me like your top level module does not contain any outputs, i.e. your logic does not drive any pins. The synthesiser will remove all logic that does not effect an output.

Hope this helps

--- Quote Start ---

Dear Sir,

I am trying one code for verilog traffic signal controller, but it seems the above error?

would you please tell me how to solve this??

the code is below:

module traffic;

parameter on = 1, off = 0, red_tics = 35,

amber_tics = 3, green_tics = 20;

reg clock, red, amber, green;

// will stop the simulation after 1000 time units

initial begin: stop_at

# 1000; $stop;

end

// initialize the lights and set up monitoring of registers

initial begin: Init

red = off; amber = off; green = off;

$display(" Time green amber red");

$monitor("%3d %b %b %b", $time, green, amber, red);

end

// task to wait for 'tics' positive edge clocks

// before turning light off

task light;

output color;

input [31:0] tics;

begin

repeat(tics) // wait to detect tics positive edges on clock

@(posedge clock); color = off;

end

endtask

// waveform for clock period of 2 time units

always begin: clock_wave

# 1 clock = 0;

# 1 clock = 1;

end

always begin: main_process

red = on;

light(red, red_tics); // call task to wait

green = on;

light(green, green_tics);

amber = on;

light(amber, amber_tics);

end

endmodule

sincerely

Kazi Mamun

Yeungnam University

South Korea

--- Quote End ---

Hi Kazi,

it is not only that you don't have specified input and outputs in your top module. There are also a lot of parts ( I have mark some red) which could not be used for synthesis. What have written is more or less a behavioral description of your design. That is fine for simulation, but you have to change your code for synthesis. Maybe somebody in the forum could recommand a verilog tutorial or a good book to start with.

Hi,

]I am really thankful for your reply,

I have tried with another code also, but problem with that code is the light changes if I turn of and turn on the switch.

but my target is simple, just implement a system that contain three light, the light will change automatically after a certain time.

would please check the code below??

module traffic1(R, G, Y, clock, reset);

output R, Y, G; // Red, Yellow, Green Signal lines

input clock, reset;

reg R, Y, G;

//state machine parameters

reg [1:0] present_state, next_state;

parameter Green = 2'b00,

Yellow = 2'b01,

Red = 2'b10,

Reset_State = 2'b11;

always @ (posedge clock)

begin

if(reset)

present_state = Reset_State;

else if (~reset)

present_state = next_state;

end

always @ (present_state)

case (present_state)

Green:

begin

G = 1'b1;

R = 1'b0;

next_state = Yellow;

end

Yellow:

begin

Y = 1'b1;

G = 1'b0;

next_state = Red;

end

Red:

begin

R = 1'b1;

Y = 1'b0;

next_state = Green;

end

Reset_State:

begin

R = 1'b0;

Y = 1'b0;

G = 1'b0;

next_state = Red;

end

endcase

endmodule

with regards

Kazi Mamun

--- Quote Start ---

Hi,

]I am really thankful for your reply,

I have tried with another code also, but problem with that code is the light changes if I turn of and turn on the switch.

but my target is simple, just implement a system that contain three light, the light will change automatically after a certain time.

would please check the code below??

module traffic1(R, G, Y, clock, reset);

output R, Y, G; // Red, Yellow, Green Signal lines

input clock, reset;

reg R, Y, G;

//state machine parameters

reg [1:0] present_state, next_state;

parameter Green = 2'b00,

Yellow = 2'b01,

Red = 2'b10,

Reset_State = 2'b11;

always @ (posedge clock)

begin

if(reset)

present_state = Reset_State;

else if (~reset)

present_state = next_state;

end

always @ (present_state)

case (present_state)

Green:

begin

G = 1'b1;

R = 1'b0;

B = 1'b0;

next_state = Yellow;

end

Yellow:

begin

Y = 1'b1;

G = 1'b0;

R = 1'b0;

next_state = Red;

end

Red:

begin

R = 1'b1;

Y = 1'b0;

G= 1'b0;

next_state = Green;

end

Reset_State:

begin

R = 1'b0;

Y = 1'b0;

G = 1'b0;

next_state = Red;

end

endcase

endmodule

with regards

Kazi Mamun

--- Quote End ---

Hi Kazi,

you forgot to define the value for some signals, which leads to infering latches. Be aware that your output changes every clock cycle. If you coonect the outputs to a LED and your clock speed is high, I 'm not sure that you can see any change.

Dear Sir,

Thanks for your reply.

to see the changing effect on DE2 board, is that okey if I increase delay with# 1000??

or what else, I can do if I want to see the change?

sincerely

Kazi Mamun

--- Quote Start ---

Dear Sir,

Thanks for your reply.

to see the changing effect on DE2 board, is that okey if I increase delay with# 1000??

or what else, I can do if I want to see the change?

sincerely

Kazi Mamun

--- Quote End ---

Hi Kazi,

unfortunately# <value> could not be used for synthesis. You have to slow down the state machine. I have added a clock divider to your design, in order to generate an enable puls for the state machine. In the example the state machine changes now only every 4th clock the state. If you need it slower you simply have to make the counter larger and chose always the MSB for the enable generator. Simulate the design and try to understand how it works.

module traffic1(R, G, Y, clock, reset);

output R, Y, G; // Red, Yellow, Green Signal lines

input clock, reset;

reg R, Y, G;

//state machine parameters

reg [1:0] present_state, next_state;

parameter Green = 2'b00,

Yellow = 2'b01,

Red = 2'b10,

Reset_State = 2'b11;

// clock divider

//

reg [3:0] divider;

reg reg1;

wire enable_state;

// counter as clock divider

always @(posedge clock) begin

if (reset) divider <= 0;

else divider <= divider + 1;

end

always @(posedge clock) begin

if (reset) reg1 <= 0;

else reg1 <= divider[3];

end

// edge detector for counter bit [3]

// Needed to make the enable signal one clock cycle long

assign enable_state = divider[3]& !reg1;

// End clock divider

always @ (posedge clock)

begin

if(reset)

present_state = Reset_State;

else if (enable_state)

present_state = next_state;

end

always @ (present_state)

case (present_state)

Green:

begin

G = 1'b1;

R = 1'b0;

Y = 1'b0;

next_state = Yellow;

end

Yellow:

begin

Y = 1'b1;

G = 1'b0;

R = 1'b0;

next_state = Red;

end

Red:

begin

R = 1'b1;

Y = 1'b0;

G = 1'b0;

next_state = Green;

end

Reset_State:

begin

R = 1'b0;

Y = 1'b0;

G = 1'b0;

next_state = Red;

end

endcase

endmodule

Thanks Pletz,

Atlast I did my required project with the code below, thanks a lot for your help.

//Verilog HDL code for intelligent Traffic system with 7seg display properties:

module traffic1(R, G, Y, pm, clock, reset,seg7);

output R, Y, G; // Red, Yellow, Green Signal lines

input clock, reset, pm;

reg R, Y, G;

output [6:0]seg7; // 7bit is output signal

reg [6:0]seg7; // Define 7bit register

//state machine parameters

reg [1:0] present_state, next_state;

parameter Green = 2'b00,

Yellow = 2'b01,

Red = 2'b10,

Reset_State = 2'b11;

// clock divider

reg [27:0] divider;

reg [24:0] divider1;

reg reg1;

reg temp;

wire enable_state;

// counter as clock divider

always @(posedge clock) begin

if (reset) divider <= 0 ;

else divider <= divider + 1;

if (reset) divider1 <= 0;

else divider1 <= divider1 + 1;

end

always @(posedge clock) begin

if (reset) reg1 <= 0;

else if (pm) reg1<= divider1[24];

else reg1 <= divider[27];

end

// edge detector for counter bit [3]

// Needed to make the enable signal one clock cycle long

always @(posedge clock) begin

if (pm) temp <= divider1[24]& !reg1;

else

temp <= divider[27]& !reg1;

end

assign enable_state = temp;

// End clock divider

always @ (posedge clock)

begin

if(reset)

present_state = Reset_State;

else if (enable_state)

present_state = next_state;

end

always @ (present_state)

case (present_state)

Green:

begin

G = 1'b1;

R = 1'b0;

//Y = 1'b0;

next_state = Yellow;

end

Yellow:

begin

Y = 1'b1;

G = 1'b0;

//R = 1'b0;

next_state = Red;

end

Red:

begin

R = 1'b1;

Y = 1'b0;

//G = 1'b0;

next_state = Green;

end

Reset_State:

begin

R = 1'b0;

Y = 1'b0;

G = 1'b0;

next_state = Red;

end

endcase

always @(pm)

begin

case(pm) // flollw operation of a

1'b1 : seg7 = 7'b0001000; //A

default : seg7 = 7'b0001100; //P

endcase

end

endmodule

--- Quote Start ---

Thanks Pletz,

Atlast I did my required project with the code below, thanks a lot for your help.

//Verilog HDL code for intelligent Traffic system with 7seg display properties:

module traffic1(R, G, Y, pm, clock, reset,seg7);

output R, Y, G; // Red, Yellow, Green Signal lines

input clock, reset, pm;

reg R, Y, G;

output [6:0]seg7; // 7bit is output signal

reg [6:0]seg7; // Define 7bit register

//state machine parameters

reg [1:0] present_state, next_state;

parameter Green = 2'b00,

Yellow = 2'b01,

Red = 2'b10,

Reset_State = 2'b11;

// clock divider

reg [27:0] divider;

reg [24:0] divider1;

reg reg1;

reg temp;

wire enable_state;

// counter as clock divider

always @(posedge clock) begin

if (reset) divider <= 0 ;

else divider <= divider + 1;

if (reset) divider1 <= 0;

else divider1 <= divider1 + 1;

end

always @(posedge clock) begin

if (reset) reg1 <= 0;

else if (pm) reg1<= divider1[24];

else reg1 <= divider[27];

end

// edge detector for counter bit [3]

// Needed to make the enable signal one clock cycle long

always @(posedge clock) begin

if (pm) temp <= divider1[24]& !reg1;

else

temp <= divider[27]& !reg1;

end

assign enable_state = temp;

// End clock divider

always @ (posedge clock)

begin

if(reset)

present_state = Reset_State;

else if (enable_state)

present_state = next_state;

end

always @ (present_state)

case (present_state)

Green:

begin

G = 1'b1;

R = 1'b0;

//Y = 1'b0;

next_state = Yellow;

end

Yellow:

begin

Y = 1'b1;

G = 1'b0;

//R = 1'b0;

next_state = Red;

end

Red:

begin

R = 1'b1;

Y = 1'b0;

//G = 1'b0;

next_state = Green;

end

Reset_State:

begin

R = 1'b0;

Y = 1'b0;

G = 1'b0;

next_state = Red;

end

endcase

always @(pm)

begin

case(pm) // flollw operation of a

1'b1 : seg7 = 7'b0001000; //A

default : seg7 = 7'b0001100; //P

endcase

end

endmodule

--- Quote End ---

Hi thwijoo,

congratulation to have your first(?) design running. Hopefully I could help you a little bit.

Bye