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Dear Sir,
Thanks for your reply.
to see the changing effect on DE2 board, is that okey if I increase delay with# 1000??
or what else, I can do if I want to see the change?
sincerely
Kazi Mamun
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Hi Kazi,
unfortunately# <value> could not be used for synthesis. You have to slow down the state machine. I have added a clock divider to your design, in order to generate an enable puls for the state machine. In the example the state machine changes now only every 4th clock the state. If you need it slower you simply have to make the counter larger and chose always the MSB for the enable generator. Simulate the design and try to understand how it works.
module traffic1(R, G, Y, clock, reset);
output R, Y, G; // Red, Yellow, Green Signal lines
input clock, reset;
reg R, Y, G;
//state machine parameters
reg [1:0] present_state, next_state;
parameter Green = 2'b00,
Yellow = 2'b01,
Red = 2'b10,
Reset_State = 2'b11;
// clock divider
//
reg [3:0] divider;
reg reg1;
wire enable_state;
// counter as clock divider
always @(posedge clock) begin
if (reset) divider <= 0;
else divider <= divider + 1;
end
always @(posedge clock) begin
if (reset) reg1 <= 0;
else reg1 <= divider[3];
end
// edge detector for counter bit [3]
// Needed to make the enable signal one clock cycle long
assign enable_state = divider[3]& !reg1;
// End clock divider
always @ (posedge clock)
begin
if(reset)
present_state = Reset_State;
else if (enable_state)
present_state = next_state;
end
always @ (present_state)
case (present_state)
Green:
begin
G = 1'b1;
R = 1'b0;
Y = 1'b0;
next_state = Yellow;
end
Yellow:
begin
Y = 1'b1;
G = 1'b0;
R = 1'b0;
next_state = Red;
end
Red:
begin
R = 1'b1;
Y = 1'b0;
G = 1'b0;
next_state = Green;
end
Reset_State:
begin
R = 1'b0;
Y = 1'b0;
G = 1'b0;
next_state = Red;
end
endcase
endmodule
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