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Honored Contributor
Honored ContributorError: Can't synthesize current design -- Top partition does not contain any logic
Dear Sir, I am trying one code for verilog traffic signal controller, but it seems the above error? would you please tell me how to solve this?? the code is below: module traffic; param...
Altera_ForumHonored Contributor
Honored ContributorLooks to me like your top level module does not contain any outputs, i.e. your logic does not drive any pins. The synthesiser will remove all logic that does not effect an output.
Hope this helps
